This invention relates to electronic circuits and more particularly to an electronic circuit which receives an input data signal and provides an output status bit indicative of the state of the input data signal received, and also provides an output delta bit which indicates whether the preset input data signal is the same as the input data signal received immediately previous to the present input data signal.
Prior art circuits for providing a status bit and a delta bit are known. One such prior art circuit utilizing a monostable multivibrator ("one shot") is shown in the schematic diagram of FIG. 1. The prior art circuit shown in FIG. 1 is used to provide a data status bit D' on output terminal 18 and a delta bit .DELTA. on output terminal 19 in response to asynchronous data signal "D". The Delta signal (.DELTA.) defines whether the present input data signal D is different from the previous input data signal (.DELTA.=1), or whether the present input data signal D is the same as the previous input data signal (.DELTA.=0). Status bit D' is equal to the present input data signal D. This information is made available to other circuitry (not shown).
In the circuit of FIG. 1, the input data signal D is read directly through the three state output buffer 16 when buffer 16 is enabled by a logical one READ enable signal applied to terminal 20. Input data signal D also is applied to the input leads of one-shots 12 and 13, each of which generates a pulse for the signal edge indicated in FIG. 1. In other words, one shot 12 provides a positive output pulse in response to each rising edge of input data signal D; one shot 13 provides a positive output pulse in response to each falling edge of input data signal D. OR gate 14 receives on its input leads the output signals from one shots 12, 13 and provides an output signal which is applied to the SET input lead of RS latch 15. RS latch 15 is reset by a logical one READ enable signal applied to terminal 20. The Q output lead of RS latch 15 is connected to the data input lead of three state buffer 17, which is enabled by a logical one READ enable signal on terminal 20. Thus, when input data signal D changes state from a logical one to a logical zero, or vice versa, a logical one pulse is provided by either one shot 12 or one shot 13 to OR gate 14, which in turn provides a logical one output pulse, causing RS latch 15 to store a logical one delta bit, indicating that the present input data signal D differs from the previous input data signal.
The schematic diagram of a typical one shot suitable for use in the circuit of FIG. 1 is shown in FIG. 2. One shot 20 includes input terminal 21 for receiving an input signal, and output terminals 27 and 29. Output terminal 27 provides a positive going pulse in response to a high to low transition of the input signal applied to input terminal 21. Conversely, output terminal 29 provides a negative going pulse in response to a low to high transition of the input signal applied to input terminal 21.
There are many disadvantages to using a one shot. Most of these can be ascribed to the variability of the delay provided by the one shot leading to an attendant lack of reliability. A one shot compares an input signal with a delayed version of itself, generating an output pulse only as long as that delay holds after the signal undergoes a given edge transition (i.e., rising edge or falling edge). This delay is often based on a number of inverter stages and/or a resistor and capacitor combination which causes the capacitor to charge up with an RC delay. However, process variations during manufacture of the one shot, such as variations in the speed of the inverter stages, variations in transistor characteristics, variations in resistor and capacitor values, variations in capacitor leakage, and the like, cause this delay to vary. Temperature, humidity, and voltage supply range also affect the delay. If the delay becomes too short, the pulse may decrease in width (time) or height (voltage), or even vanish altogether, causing any circuit relying on that pulse to fail to operate properly. Conversely, if the one shot delay is excessively long, it will extend unwanted into a later timing period. One shots are sometimes used to provide a relatively long output pulse in response to a relatively short input pulse, and they are thus very susceptible to error caused by noise. Since the one shot fires its output pulse immediately, it is also possible that some circuit further along may not be ready for it, and will thus miss the output pulse altogether.
Another problem exists with the prior art circuit of FIG. 1. When three state buffers 16, 17 are enabled during a read operation (status bit D' and delta bit .DELTA. being read by external circuitry connected to terminals 18 and 19, respectively) and asynchronous input data signal D changes during this read operation then the corresponding data bus status bit D' changes, passing an undefined value (e.g., a voltage level between the voltage levels associated with a logical one and a logical zero) to the external circuitry. Furthermore, when three state buffers 16, 17 are latched, a race condition may result: when input data signal D changes shortly before a logical one READ signal, the new value of input data signal D passes through three state latch 16, while the new delta signal (which must equal one) may not yet be generated by one shots 12, 13, OR gate 14, and latch 15. Then, a delta=0 signal is provided on output terminal 19, indicating no change in input data, while the new (changed data signal D is provided on output terminal 18, creating a contradiction. Furthermore, if input data signal D changes during a read operation, RS latch 15 is still being reset by the READ signal. Then, since the one shot pulses have already been generated, during the next read operation, the delta bit is a logical zero (no change) and the data status bit D' is the new input data signal D, a contradiction.
Accordingly, prior art status register and delta circuits have been found to be unsatisfactory.